The present disclosure relates generally to integrated circuits, such as processors and/or field-programmable gate arrays (FPGAs). More particularly, the present disclosure relates to improving scalability (e.g., component scalability, product variation scalability) of integrated circuits using modular periphery tiles.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it may be understood that these statements are to be read in this light, and not as admissions of prior art.
Modern electronics, such as computers, portable devices, network routers, data centers, Internet-connected appliances, and more, tend to include at least one integrated circuit device. Integrated circuit devices may take on a variety of forms, including processors (e.g., central processing units (CPUs)), memory devices, and programmable devices (e.g., FPGA), to name only a few examples. The programmable devices, in particular, may include a programmable fabric of logic (e.g., configurable logic blocks (CLBs)) that may be programmed (e.g., configured) and reprogrammed (e.g., reconfigured) after manufacturing to provide a wide variety of functionality based on a circuit design.
To facilitate operations, the programmable device may include a variety of periphery intellectual property cores (IPs) near and around the programmable fabric. For example, a double data rate (DDR) IP may be placed on a shoreline of the programmable fabric to avoid consuming excess routing circuitry of the programmable fabric. Due to a restricted amount of shoreline however, design compromises may occur when determining the number of and type of periphery IP to include around the shoreline. This may result in reduced device performance for certain product variations and reduced overall scalability (e.g., component scalability, product scalability) of the programmable device.